Address mapping can have a significant impact on the rate at which the mapped data can be accessed for read and write operations. As an example, in a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) interface of a core logic chipset for supporting a CPU (Central Processing Unit) of a computing platform, there can be two channels of memory. Data is interleaved across the channels on a quadword basis.
Each memory channel is a quadword (QW) wide. A quadword is four words and a word is two bytes, so a quadword is eight consecutive bytes of data. This is a typical organization for a dual channel memory subsystem for a CPU supporting a 64-bit bus. Typically, as an agent reads or writes, walking through memory, it alternates from one channel to the other. So, for example, QW0 is from channel A and QW1 is from channel B. QW2 is from channel A and QW3 is from channel B. This alternating memory map optimizes memory access speed for a connected CPU because it minimizes the effects of delays within the SDRAM modules. It also provides the quadwords in an order that is typically the best order for the CPU. QWs 0 and 1 are fetched first and these are typically the first quadwords that the CPU wants.
These two channels of memory with this alternating mapping can be used to interface external memory to any of the devices coupled to or integrated on the chipset. While this mapping may be optimal for a CPU, it is far less than optimal for some of the other possible connected or integrated components. An integrated graphics controller typically also requests data in pairs of two QWs.
An integrated graphics controller can request a pair of QWs at one address and another pair of QWs 64, 128 or 256 bytes away from the first pair. The traditional organization in which consecutive QWs are interleaved across channels prevents full use of the available memory access bandwidth for such requests.